1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit technology, and especially relates to a technology of efficiently providing wires from a device package having bottom electrodes, such as a BGA (Ball Grid Array), to a printed wiring board (PWB), on which the device package is mounted.
2. Description of the Related Art
Device packages, i.e., semiconductor integrated circuits, are required to provide a great number of pins in small dimensions for high-density mounting. In concert with the miniaturization (high-density) of the device packages, high-density wiring of the PWB is required. However, it is often difficult to provide a sufficient number of connections between elements within a desired small space.
In order to pull out wiring from the inner positions of the device package (an electronic part) having bottom electrodes, such as a BGA, the number of layers of the PWB must be increased, wires have to be made fine, and a high degree of freedom for inter-layer wiring (build-up, and the like) is required. Further, it is predicted that connections between the elements will become impossible in the near future even if the build-up technology is used.
Conventionally, as Patent Reference 1 proposes, an “auxiliary device package for wiring” is used such that wiring to/from external terminals (bottom electrodes, etc.) arranged at the central part of the BGA device package is enabled, and the number of layers of the PWB is increased where wiring is dense so that the wiring difficulty is alleviated.
Nevertheless, with the conventional technology, the auxiliary device package for wiring is additionally required, and an increased number of layers in the PWB is required, which raise costs and increase dimensions.
[Patent reference 1] JPA 11-68026